Imec and Cadence Design Systems, Inc. announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout.   The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell libr...